4/97 precision phase locked frequency control system crystal oscillator programmable reference frequency dividers phase detector with absolute frequency steering digital lock indicator double edge option on the frequency feedback sensing amplifier two high current op-amps 5v reference output phase locked frequency controller uc1633 uc2633 uc3633 features the uc1633 family of integrated circuits was designed for use in phase locked frequency control loops. while optimized for precision speed control of dc motors, these devices are universal enough for most ap- plications that require phase locked control. a precise reference fre- quency can be generated using the devices high frequency oscillator and programmable frequency dividers. the oscillator operates using a broad range of crystals, or, can function as a buffer stage to an external frequency source. the phase detector on these integrated circuits compares the refer- ence frequency with a frequency/phase feedback signal. in the case of a motor, feedback is obtained at a hall output of other speed detection device. this signal is buffered by a sense ampilfier that squares up the signal as it goes into the digital phase detector. the phase detector re- sponds proportionally to the phase error between the reference and the sense amplifier output. this phase detector includes absolute fre- quency steering to provide maximum drive signals when any frequency error exists. this feature allows optimum start-up and lock times to be realized. two op-amps are included that can be configured to provide necessary loop filtering. the outputs of the op-amps will source or sink in excess of 16ma, so they can provide a low impedence control signal to driving circuits. additional features include a double edge option on the sense amplifier that can be used to double the loop reference frequency for increased loop bandwidths. a digital lock signal is provided that indicates when there is zero frequency error, and a 5v reference output allows dc op- erating levels to be accurately set. description block diagram 1
parameter test conditions min. typ. max. units supply current +v in = 15v 20 28 ma reference output voltage (v ref ) 4.75 5.0 5.25 v load regulation i out = 0v to 7ma 5.0 20 mv line regulation +v in = 8v to 15v 2.0 20 mv short circuit current v out = 0v 12 30 ma oscillator dc voltage gain oscillator input to oscillator output 12 16 20 db input dc level (v ib ) oscillator input pin open, t j = 25c 1.15 1.3 1.45 v input impedance (note 3) v in = v ib 0.5v, t j = 25 c 1.3 1.6 1.9 k w output dc level oscillator input pin open, t j = 25c 1.2 1.4 1.6 v maximum operating frequency 10 mhz dividers maximum input frequency input = 1v pp at oscillator input 10 mhz div. 4/5 input current input = 5v (div. by 4) 150 500 m a input = 0v (div. by 5) -5.0 0.0 5.0 m a div. 4/5 threshold 0.5 1.6 2.2 v note 3: these impedence levels will vary with t j at about 1700ppm/c uc1633 uc2633 uc3633 input supply voltage (+v in ) . . . . . . . . . . . . . . . . . . . . . . . . +20v reference output current . . . . . . . . . . . . . . . . . . . . . . . . -30ma op-amp output currents . . . . . . . . . . . . . . . . . . . . . . . . 30ma op-amp input voltages . . . . . . . . . . . . . . . . . . . . . -.3v to +20v phase detector output current . . . . . . . . . . . . . . . . . . . 10ma lock indicator output current . . . . . . . . . . . . . . . . . . . . +15ma lock indicator output voltage . . . . . . . . . . . . . . . . . . . . . . +20v divide select input voltages . . . . . . . . . . . . . . . . . -.3v to +10v double edge disable input voltage . . . . . . . . . . . . -.3v to +10v oscillator input voltage . . . . . . . . . . . . . . . . . . . . . . -.3v to +5v sense amplifier input voltage . . . . . . . . . . . . . . . . .3v to +20v power dissipation at t a = 25c (note 2 . . . . . . . . . . . 1000mw power dissipation at t c = 25c (note 2) . . . . . . . . . . . 2000mw operating junction temperature . . . . . . . . . . . -55c to +150c storage temperature . . . . . . . . . . . . . . . . . . . . -65c to +150c lead temperature (soldering, 10 seconds) . . . . . . . . . . 300c absolute maximum ratings connection diagrams package pin function function pin n/c 1 div 4/5 input 2 div 2/4/8 input 3 lock indicator output 4 phase detector output 5 n/c 6 dbl edge disable input 7 sense amp input 8 5v ref output 9 loop amp inv input 10 n/c 11 loop amp output 12 aux amp non-inv input 13 aux amp inv input 14 aux amp output 15 n/c 16 +v in 17 osc output 18 osc input 19 ground 20 plcc-20 (top view) q package note1: voltages are referenced to ground, (pin 16). currents are positive into, negative out of, the specified terminals. note 2: consult packaging section of databook for thermal limi- tations and considerations of package. dil-16 (top view) j or n package electrical characteristics: (unless otherwise stated, these specifications apply for t a = 0c to +70c for the uc3633, -25 c to +85 c for the uc2633, -55c to +125c for the uc1633, +v in = 12v; t a =t j .) 2
parameter test conditions min. typ. max. units dividers (cont.) div. 2/4/8 input current input = 5v (div. by 8) 150 500 m a input = 0v (div. by 2) -500 -150 m a div. 2/4/8 open circuit voltage input current = 0 m a (div. by 4) 1.5 2.5 3.5 v div. by 2 threshold 0.20 0.8 v div. by 4 threshold 1.5 3.5 v div. by 8 threshold volts below v ref 0.20 0.8 v sense amplifier threshold voltage percent of v ref 27 30 33 % threshold hysteresis 10 mv input bias current input = 1.5v -1.0 -0.2 m a double edge disable input input current input = 5v (disabled) 150 500 m a input = 0v (enabled) -5.0 0.0 5.0 m a threshold voltage 0.5 1.6 2.2 v phase detector high output level positive phase/freq. error, volts below v ref 0.2 0.5 v low output level negative phase/freq. error 0.2 0.5 v mid output level zero phase/freq. error, percent of v ref 47 50 53 % high level maximum source current v out = 4.3v 2.0 8.0 ma low level maximum sink current v out = 0.7v 2.0 5.0 ma mid level output impedance (note 3) i out = -200 to +200 m a, t j = 25c 4.5 6.0 7.5 k w lock indicator output saturation voltage freq. error, i out = 5ma 0.3 0.45 v leakage current zero freq. error, v out = 15v 0.1 1.0 m a loop amplifier non inv. reference voltage percent of v ref 47 50 53 % input bias current input = 2.5v -0.8 -0.2 m a avol 60 75 db psrr +v in = 8v to 15v 70 100 db short circuit current source, v out = 0v 16 35 ma sink, v out = 5v 16 30 ma auxiliary op-amp input offset voltage v cm = 2.5v 8 mv input bias current v cm = 2.5v -0.8 -0.2 m a input offset current v cm = 2.5v .01 0.1 m a avol 70 120 db psrr +v in = 8v to 15v 70 100 db cmrr v cm = 0v to 10v 70 100 db short circuit current source, v out = 0v 16 35 ma sink, v out = 5v 16 30 ma note 3: these impedence levels will vary with t j at about 1700ppm/c uc1633 uc2633 uc3633 electrical characteristics (cont.): (unless otherwise stated, these specifications apply for t a = 0c to +70c for the uc3633, -25 c to +85 c for the uc2633, -55c to +125c for the uc1633, +v in = 12v; t a =t j .) 3
uc1633 uc2633 uc3633 determining the oscillator frequency the frequency at the oscillator is determined by the de- sired rpm of the motor, the divide ratio selected, the number of poles in the motor, and the state of the double edge select pin. f osc (hz) = (divide ratio) (motor rpm) (1/60 sec/min) (no. of rotor poles/2) (x 2 if pin 5 low) the resulting reference frequency appearing at the phase detector inputs is equal to the oscillator frequency divided by the selected divide ratio. if the double edge option is used, (pin 5 low), the frequency of the sense amplifier in- put signal is doubled by responding to both the rising and falling edges of the input signal. using this option, the loop reference frequency can be doubled for a given motor rpm. application and operating information recommended oscillator configuration using at cut quartz crystal external reference frequency input method for deriving rotation feedback signal from analog hall effect device *this signal may require filtering if chopped mode drive scheme is used. 4
phase detector operation the phase detector on these devices is a digital circuit that responds to the rising edges of the detectors two in- puts. the phase detector output has three states: a high, 5v state, a low, 0v state, and a middle, 2.5v state. in the high and low states the output impedance of the detector is low and the middle state output impedence is high, typi- cally 6.0k w . when there is any static frequency difference between the inputs, the detector output is fixed at its high level if the +input (the sense amplifier signal) is greater in frequency, and fixed at its low level if the -input (the refer- ence frequency signal) is greater in frequency. when the frequencies of the two inputs to the detector are equal, the phase detector switches between its middle state and either the high or low states, depending on the relative phase of the two signals. if the +input is leading in phase then, during each period of the input frequency, the detector output will be high for a time equal to the time dif- ference between the rising edges of the inputs, and will be at its middle level for the remainder of the period. if the phase relationship is reversed, then the detector will go low for a time proportional to the phase difference of the inputs. the resulting gain of the phase detector. k?, is 5v/4 p radians or about 0.4v/radian. the dynamic range of the detector is 2 p radians. the operation of the phase detector is illustrated in the figures below. the upper figure shows typical voltage waveforms seen at the detector output for leading and lagging phase conditions. the lower figure is a state dia- gram of the phase detector logic. in this figure, the circles represent the 10 possible states of the logic, and the con- necting arrows represent the transition events/paths to and from these states. transition arrows that have a clock- wise rotation are the result of a rising edge on the +input, and conversely, those with counter-clockwise rotation are tied to the rising edge of the -input signal. the normal operational states of the logic are 6 and 7 for positive phase error, 1 and 2 for a negative phase error. states 8 and 9 occur during positive frequency error, 3 and 4 during negative frequency error. states 5 and 10 occur only as the inputs cross over from the frequency er- ror to a normal phase error only condition. the level of the phase detector output is determined by the logic state as defined in the state diagram figure. the lock indicator out- put is high, off, when the detector is in states 1, 2, 6, or 7. uc1633 uc2633 uc3633 typical phase detector output waveforms phase detector state diagram application and operation information 5
uc1633 uc2633 uc3633 application and operation information n out n in ( s ) = r 3 r 1 1 + s w z 1 + s w p w p = 1 r 2 c 1 w z = 1 ( r 1 + r 2 ) c 1 where: | d v out | = |v out - 2.5v| and v out = dc operating voltage at loop amplifier output during phase lock if: (v out - 2.5) > 0, r 4 goes to 0v (v out - 2.5) < 0, r 4 goes to 5.0v * the static phase error of the loop is easily adjusted by adding resistor, r 4 , as shown. to lock at zero phase error r 4 is determined by: r 4 = 2.5v r 3 | d v out | n out n in ( s ) = 1 1 + s 2 z w n + s 2 w n 2 w n = 1 ? ````````` r 1 r 2 c 1 c 2 z = 1 2 q = 1 2 ? `` c 2 c 1 r 1 + r 2 ? ````` r 1 r 2 note: with r 1 = r 2 , z = ? `` c 2 c 1 reference filter design aid - gain response reference filter design aid - phase response reference filter configuration suggested loop filter configuration 6
design example uc1633 uc2633 uc3633 bode plots - design example open loop response 1.) k lf (s) k rf (s) 2.*) n k f g pd k t s 2 j 3.) combined overall open loop response where: k lf (s) = loop filter response k rf (s) = reference filter response n = 4 (using double edge sensing with 4 pole motor) k f = phase detector gain (.4v/rad) g pd = power stage transductance (1a/v) k t = motor torque constant (.022nm/a) j = motor moment of inertia (.0015nm/a - sec 2 ) s = 2 p jf *note: for a current mode driver the electrical time constant, l m / r m, of the motor does not enter into the small signal response. if a voltage mode drive scheme is used, then the asymptote, plotted as 2 above, can be approximated by: n k f k pd k t s 2 j r m if: r m > k t ? `` l m j and, k t 2 2 p j r m < f < r m 2 p l m here: k pd = voltage gain of driver stage r m = motor winding resistance l m = motor winding inductance application and operation information unitrode corporation 7 continental blvd. merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 7
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